1. Field of the Invention
The present invention relates generally to an electronic circuit for serializing data from an incoming parallel data stream.
2. Description of the Related Art
The serializer is a key component in serial digital communication applications. In such systems, serializers are used to convert multi-bit low speed parallel data into high-speed serial data. For high-frequency applications, completely full-swing CMOS serializers are not considered due to their high power consumption. To reduce power, the high-speed blocks are designed using a differential logic family such as Current Mode Logic, but if the whole serializer is designed using a differential logic family, power consumption is still high. Hence, a hybrid combination of full-swing logic (at low frequency) and differential logic (at high frequency) is preferred. The usage of two entirely different logic families, however, poses a significant signal reliability problem at the interface between the two logic families. To alleviate this problem, careful designing is required, which requires more design resources and time. Also, differential circuits have additional overhead of current-source reference circuits to provide reference for the tail current in the differential logic.
FIG. 1 shows an exemplary serializer, which recieves input signals 120, 122, 124, and 126. Each input bit exhibits either a high or low voltage indicative of either a high or low bit value. The input data is received in parallel at a frequency of 625 MHz. The serializer of FIG. 1 includes three instances of circuit blocks 130 (shown as 130A, 130B, and 130C), each having two flip-flops 132 and a multiplexer 134 to generate a single output signal containing data of both input signals at twice the input frequency. In a first frequency domain of f/4, e.g., 625 MHz, input signals 120 and 122 are multiplexed to output signal 140 by circuit block 130A, and input signals 124 and 126 are multiplexed to output signal 144 by circuit block 130B. Output signals 140, 144 are taken as input signals to circuit block 130C in the f/2 domain having a frequency of f/2, e.g., 1.25 GHz. Output signal 150 of circuit block 130C is passed through a flip-flop 152, which is in the frequency domain of f, e.g., 2.5 GHz and provides an output signal 154 of serialized data having a frequency 4 times that of input signals 120, 122, 124, 126.
This approach to serializing data has significant disadvantages. First, this design contains three levels of flip-flop logic, which operate at frequencies of f/4, f/2, and f as described above. Four operate at f/4 frequency, two operate at f/2 frequency, and one flip-flop operates at f frequency. The total switching power due to clocks is given by:
                              Total          ⁢                                                            ⁢                                                          ⁢          Clock          ⁢                                          ⁢          Switching          ⁢                                          ⁢          Power                =                ⁢                              4            ·                          (                              C                ⁢                                                                  ⁢                                  V                  2                                ⁢                                  f                  /                  4                                            )                                +                      2            ·                          (                              C                ⁢                                                                  ⁢                                  V                  2                                ⁢                                  f                  /                  2                                            )                                +                      1            ·                          (                              C                ⁢                                                                  ⁢                                  V                  2                                ⁢                f                            )                                                                        =                    ⁢                      3            ⁢                                                  ⁢            C            ⁢                                                  ⁢                          V              2                        ⁢            f                          ,            where C is the input capacitance of the clock line of a flip-flop, f is the frequency of the clock on the output flip-flop 152, and V is power supply voltage. Note that this equation is an approximate equation since the power consumed by the multiplexer is not incorporated. In general for a 2N:1 serializer, total clock switching power=(N+1)CV2f.
The primary concern in using a full-swing serializer for high-speed applications is power. Any improvement in the serializing technique that addresses power would greatly improve the design cycle time and total system power.